Semiconductor device and method of manufacturing the same

ABSTRACT

To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2017-161043 filed onAug. 24, 2017 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and a method ofmanufacturing the same, which can be applied to, for example, thesemiconductor device having an OPM electrode and the method ofmanufacturing the same.

Recently, based on demands for improving reliability of semiconductordevice and so on, there is proposed a structure obtained by forming apad electrode containing mainly aluminum on a semiconductor substrate,forming a conductive layer called an OPM (Over Pad Metal) electrode onthe pad electrode, and coupling an external coupling terminal such as aclip or a bonding wire to the OPM electrode.

For example, Japanese Unexamined Patent Application Publication No.2000-235964 discloses a technology of forming an OPM electrode made of anickel film and a gold film on the pad electrode containing mainlyaluminum using electroless plating.

Moreover, Japanese Unexamined Patent Application Publication No.2007-227412 discloses an IGBT module including a diode and an IGBT(Insulated Gate Bipolar Transistor) coupled in antiparallel with eachother.

Furthermore, “Zincate Treatment and Electroless Ni—P Plating on AlSingle-Crystal Surface,” Journal of The Surface Finishing Society ofJapan, Vol. 48, No. 8, p. 820-825, 1997 discloses a technology ofobtaining a (100) surface, a (110) surface, and a (111) surface fromsingle-crystal aluminum (Al) and then performing a zincate treatmentusing an aqueous solution containing zinc (Zn) and an electroless Ni—Pplating treatment on these surfaces. The above-mentioned documentdescribes study on how the differences among the crystal surfacesaffects the size of deposited Zn particles and growth of an Ni—P platingfilm.

SUMMARY

As disclosed in “Zincate Treatment and Electroless Ni—P Plating on AlSingle-Crystal Surface,” Journal of The Surface Finishing Society ofJapan, Vol. 48, No. 8, p. 820-825, 1997, when zincate treatment isperformed on the (100) surface of aluminum, there is a problem thatrelatively large Zn particles are deposited and the thickness of theNi—P plating film formed thereon may not be uniform. Because the surfaceof the Ni—P plating film is rough and does not present a dense film,moisture may easily enter from the outside of the semiconductor device.This may cause such a problem that corrosion occurs to an interfacebetween the Ni—P plating film and an aluminum film, which increasespossibility that the Ni—P plating film would be separated from thealuminum film. In such a case, if the OPM electrode made of the platingfilm of nickel or the like is formed on the pad electrode containingmainly aluminum as described in Japanese Unexamined Patent ApplicationPublication No. 2000-235964, the OPM electrode is easily removed fromthe pad electrode, thereby reducing reliability of the semiconductordevice.

Other problems and novel features will become apparent from thefollowing description and accompanying drawings.

Outline of representative one of embodiments disclosed herein is brieflydescribed below.

According to a semiconductor device and a method of manufacturing thesame of one embodiment, the semiconductor device includes: a padelectrode that is formed over a semiconductor substrate and includes afirst conductive film and a second conductive film formed over the firstconductive film; and a plating film that is formed over the secondconductive film and serves to be coupled to an external connectionterminal.

According to one embodiment, it is possible to improve reliability ofthe semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor device according toa first embodiment;

FIG. 2 is a s cross-sectional view of the semiconductor device during amanufacturing process that follows FIG. 1;

FIG. 3 is a s cross-sectional view of the semiconductor device duringthe manufacturing process that follows FIG. 2;

FIG. 4 is a s cross-sectional view of the semiconductor device duringthe manufacturing process that follows FIG. 3;

FIG. 5 is a s cross-sectional view of the semiconductor device duringthe manufacturing process that follows FIG. 4;

FIG. 6 shows a process flow indicative of the manufacturing process ofthe semiconductor device that follows FIG. 5;

FIG. 7 is a cross-sectional view of the semiconductor device during themanufacturing process that follows FIG. 6;

FIG. 8 is a schematic view of the semiconductor device according to thefirst embodiment and an IGBT in a modularized form;

FIG. 9 is a plan view showing the semiconductor device of FIG. 8 in amounted state;

FIG. 10 is a cross-sectional view taken along a line A-A in FIG. 9;

FIG. 11 is a cross-sectional view of a main part of the semiconductordevice of a third embodiment;

FIG. 12 is a cross-sectional view of the semiconductor device during themanufacturing process that follows FIG. 11;

FIG. 13 is a cross-sectional view of the semiconductor device during themanufacturing process that follows FIG. 12; and

FIG. 14 is a plan view showing the semiconductor device of FIG. 13 inthe mounted state.

DETAILED DESCRIPTION

In the following embodiments, although explanation is given with respectto each section or each embodiment as needed for convenience, thesections or embodiments are not irrelevant to each other but one may bea part or all of a modification, detailed description, or supplementaryexplanation of another, unless otherwise specified.

Moreover, in the following embodiments, when a number (including numberof pieces, numerical value, amount, range and the like) of an element isreferenced, it is not limited to the specific number but may be more orless than the specific number, unless otherwise specified or explicitlylimited to the specific number in principle.

Furthermore, in the following embodiments, components (including elementsteps) are not necessarily essential unless otherwise specified orexplicitly essential in principle.

Similarly, in the following embodiments, when a shape, positionalrelationship, or the like of the component is referenced, it includessubstantially approximate or similar shape or the like unless otherwisespecified or explicitly inapplicable in principle. This also applies tothe numerical values and ranges described above.

Throughout the figures for illustrating the embodiments, like referencenumerals designate like parts in principle and the description thereofis not repeated. It is to be noted that a plan view may be hatched forbetter understanding.

First Embodiment

With reference to FIGS. 1 to 7, explanation is given about asemiconductor device and a method of manufacturing the same according toa first embodiment. This embodiment presents a diode DI used as a superfast recover diode (Fast Recovery Diode), for example, as asemiconductor element mounted on the semiconductor device.

As shown in FIG. 1, a substrate is prepared first that has n-typeconductivity and includes a semiconductor such as silicon. The substrateconfigures a drift region DR of the diode DI. An impurity region ANhaving p-type conductivity is then formed near a surface of the driftregion DR by ion implantation or the like. The impurity region ANconfigures an anode region of the diode DI.

This embodiment describes a configuration including the drift region DRand the anode region AN as a semiconductor substrate SUB.

Here, a crystal surface on a surface of the drift region DR is a (001)surface. Because a silicon substrate having the (001) surface iscommonly used, the manufacturing cost can be suppressed compared withpreparing a substrate having another crystal surface. Moreover, thecrystal surface on the surface of the anode region AN formed over thesurface of the drift region DR is also the (001) surface. That is, thecrystal surface on the surface of the semiconductor substrate SUB is the(001) surface.

Moreover, FIG. 1 shows a state in which an insulating film IF1 is formedover the surface of the semiconductor substrate SUB as a thin naturaloxide film or a foreign matter.

Next, as shown in FIG. 2, the surface of the semiconductor substrate SUBis subjected to, for example, a reactive dry etching treatment using agas containing carbon tetrafluoride (CF4) and a wet etching treatmentusing a cleaning liquid containing hydrogen fluoride (HF) as a cleaningtreatment. The cleaning treatment removes the insulating film IF1deposited over the surface of the semiconductor substrate SUB includingthe anode region AN. The cleaning treatment is performed primarily forreducing forward resistance of the diode DI, and thus for reducingcontact resistance between the semiconductor substrate SUB and a padelectrode PD that will be formed later.

Next, as shown in FIG. 3, a conductive film AL1 containing mainlyaluminum and doped with a small amount of silicon is formed over thesemiconductor substrate SUB by, for example, sputtering. The thicknessof the conductive film AL1 is about 2,500 nm. Temperature of formationof the conductive film AL1 by sputtering is about room temperature (23°C.) to 200° C., and more preferably about 150° C. It is to be noted thatthe reason why the conductive film AL1 is doped with a small amount ofsilicon is to prevent an interface between the conductive film AL1 andthe semiconductor substrate SUB from having a spike shape.

Here, when the conductive film AL1 is an aluminum film, forming thealuminum film by the above-mentioned sputtering makes the crystalstructure of the aluminum film a face-centered cubic structure (FCC:Face-Centered Cubic), and therefore the conductive film AL1 has the(111) surface or close-packed surface on almost all of its surfaces ifnot affected by its base. However, the conductive film AL1 according tothe embodiment is formed taking over the crystal surface of thesemiconductor substrate SUB, and thus the crystal surface on the surfaceof the conductive film AL1 is the (001) surface. This is because thestep of forming the conductive film AL1 is performed immediately afterthe cleaning treatment illustrated in FIG. 2 and therefore theconductive film AL1 tends to take over the crystal surface on thesurface of the semiconductor substrate SUB during the forming step.Moreover, with the diode DI according to the embodiment, for the purposeof reducing the forward resistance, a barrier metal film includingtitanium nitride having higher resistance than that of the conductivefilm AL1 is not formed between the conductive film AL1 and thesemiconductor substrate SUB but the conductive film AL1 is formeddirectly over the semiconductor substrate SUB.

In the light of crystallography, with regard to a cubic crystal, the(001) surface is equivalent to the (100) surface and a (010) surface asa crystal surface. Therefore, the (001) surface of the conductive filmAL1 according to the embodiment is treated as a crystal surfaceequivalent to the (100) surface disclosed in “zincate Treatment andElectroless Ni—P Plating on Al Single-Crystal Surface,” Journal of TheSurface Finishing Society of Japan, Vol. 48, No. 8, p. 820-825, 1997.Here, as described in the above-mentioned document, there is a problemthat, when the zincate treatment is performed on the (001) surface ofthe conductive film AL1 in the following step, zinc particles having arelatively large size are deposited, resulting in uneven thickness ofthe plating film of nickel or the like formed in the following step.This may cause separation between the plating film and the conductivefilm AL1, thereby reducing reliability of the semiconductor device.

In other words, unless the cleaning treatment is performed as in thisembodiment, the thin natural oxide film or the foreign matter is presentover the surface of the semiconductor substrate SUB. If the conductivefilm AL1 is formed in such a state, the conductive film AL1 can hardlytake over the crystal surface on the surface of the semiconductorsubstrate SUB, making it easier for the crystal surface other than the(001) surface to be formed over the surface of the conductive film AL1.However, to reduce resistance of the diode DI, it is desirable toperform the cleaning treatment to remove the thin natural oxide film orthe foreign matter. This may make the crystal surface on the surface ofthe conductive film AL1 configuring the pad electrode PD the (001)surface.

Therefore, the inventors have come up with a method of reducingresistance of the diode DI and making the crystal surface on the surfaceof the pad electrode PD different from the (001) surface by performingthe cleaning treatment.

FIG. 4 is a cross-sectional view of the method of manufacturing thesemiconductor device that follows FIG. 3.

As described with reference to FIG. 3, the crystal surface on thesurface of the conductive film AL1 is the (001) surface. In this state,as shown in FIG. 4, an insulating film BIF is formed over the conductivefilm AL1 first. The insulating film BIF is formed by exposing thesurface of the conductive film AL1 to an atmosphere containing oxygen,e.g. by once taking out the semiconductor substrate SUB from asputtering device and exposing the semiconductor substrate SUB to theatmospheric air at room temperature (23° C.). That is, the insulatingfilm BIF includes an oxide of a material that forms the conductive filmALL such as aluminum oxide. The thickness of the insulating film BIFranges from 0.5 nm to 4.0, and more preferably from 1.0 nm to 3.0 nm.

Next, a conductive film AL2 containing mainly aluminum, for example, andalso doped with silicon is formed over the insulating film BIF by thesputtering, for example. The thickness of the conductive film AL2 isabout 2,500 nm. The temperature for forming the conductive film AL2 bythe sputtering is between about the room temperature (23° C.) and 200°C., and more preferably about 150° C.

Now, due to the insulating film BIF formed between the conductive filmAL2 and the conductive film ALL the conductive film AL2 does not takeover the (001) surface that is the crystal surface on the surface of theconductive film AL1 and thus it can be formed with the crystal surfacedifferent from the (001) surface.

In this embodiment, at the initial stage of forming the conductive filmAL2 by the sputtering, the crystal surface on the surface of theconductive film AL2 is predominantly the (111) surface. Specifically,90% or more of the surface area of the conductive film AL2 is the (111)surface. In this manner, even if the (110) surface remains on a part ofthe conductive film AL2 after the initial stage of film formation,because particles on the (110) surface are covered by the particles ofthe (111) surface that configures the most part of the conductive filmAL2 in the subsequent stage of film formation by the sputtering, themost part of the surface of the conductive film AL2 eventually becomesthe (111) surface. Preferably, 90% or more of the surface of theconductive film AL2 is finally the (111) surface, and more preferably99% or more of the surface of the conductive film AL2 is finally the(111) surface.

In this manner, by forming the thin insulating film BIF over the surfaceof the conductive film AL1 having the (100) crystal surface, the crystalsurface on the surface of the conductive film AL2 to be the surface ofthe pad electrode PD can be the (111) surface. That is, the insulatingfilm BIF is an orientation blocking film serving as a film for blockingorientation of crystal.

Although the embodiment shows the pad electrode PD having a two-layerstructure of the conductive film AL1 and the conductive film AL2, thepad electrode PD may have three or more layers by further forming aninsulating film such as the insulating film BIF over the conductive filmAL2 and subsequently forming a conductive film such as the conductivefilm AL2 thereon.

Moreover, as described above, the thickness of the insulating film BIFis no less than 0.5 nm and no more than 4.0 nm, and more preferably noless than 1.0 nm and no more than 3.0 nm. This is the thickness rangefor the conductive film AL2 not to take over the crystal surface of theconductive film AL1 and for sufficient conductivity to be guaranteedbetween the conductive film AL2 and the conductive film ALL That is,because voltage of millions of volts is applied to such a diode DI asdescribed in this embodiment, the insulating film BIF having thethickness as described above does not affect properties of the diode DI.

Next, as shown in FIG. 5, the pad electrode PD containing mainly theconductive film AL2 and the conductive film AL1 is formed by patterningthe conductive film AL2, the insulating film BIF, and the conductivefilm AL1 using photolithography and dry etching.

An insulating film IF2 including an organic resin such as photosensitivepolyimide is then formed over the semiconductor substrate SUB so as tocover the pad electrode PD. Then, an opening OP1 exposing a part of thepad electrode PD is formed over the insulating film IF2 by selectivelyexposing the insulating film IF2 to light. It is to be noted that amaterial for the insulating film IF2 may be inorganic insulating filmsuch as silicon oxide or silicon nitride instead of the organic resindescribed above.

FIG. 6 illustrates a process flow to the step at which a conductivelayer OPM is formed as in FIG. 7 to be described later, showing a plasmaetching treatment S11 and plating treatments S12 to S20 to be performedon the pad electrode PD. In this embodiment, the plating treatment isdescribed to include surface treatments S12 to S14, zincate treatmentsS15 to S17, and electroless plating treatments S18 to S20. After eachprocess at S12 to S20, a pure water cleaning treatment may be performed.

Before conductive films PF1 to PF3 that are plating films are formedover the pad electrode PD by the electroless plating treatments S18 toS20, the plasma etching treatment S11 and the surface treatments S12 toS14 are performed on the surface of the pad electrode PD. The plasmaetching treatment S11 and the surface treatments S12 to S14 areperformed to remove the natural oxide film, the grease, the foreignmatter, and the like present over the surface of the pad electrode PD.

As indicated at Step S11 in FIG. 6, the plasma etching treatment isperformed first on the surface of the conductive film AL2 using inertgas such as argon (Ar). The natural oxide film over the surface of theconductive film AL2 is removed by the plasma etching treatment.

Next, the plating treatment is performed on the surface of theconductive film AL2 in the order of surface treatments S12 to S14,zincate treatments S15 to S17, and electroless plating treatments S18 toS20.

As indicated at Step S12 in FIG. 6, the degreasing treatment isperformed on the surface of the conductive film AL2 using a weakalkaline aqueous solution containing sodium hydroxide or the like. Thegrease over the surface of the conductive film AL2 and the natural oxidefilm over the surface of the conductive film AL2 are primarily removedby the degreasing treatment.

Next, as indicated at Step S13 in FIG. 6, the etching treatment isperformed using an alkaline aqueous solution containing, for example,copper (Cu). The etching treatment is performed to remove aluminum oxidepresent near the surface of the conductive film AL2, and it is effectivewhere the conductive film AL2 is made of aluminum doped with silicon asin this embodiment. That is, by dissolving aluminum oxide present nearthe surface of the conductive film AL2 with the alkaline aqueoussolution and substituting the aluminum surface with copper having astandard electrode potential higher than that of aluminum, it ispossible to effectively reduce aluminum oxide present near the surfaceof the conductive film AL2.

Next, as indicated at Step S14 in FIG. 6, an acid cleaning is performedon the surface of the conductive film AL2 using an aqueous solutioncontaining, for example, nitric acid. The acid cleaning allows for thecopper substituted at Step S13 to be dissolved in the aqueous solutioncontaining nitric acid and for removing copper from the surface of theconductive film AL2.

Next, as indicated at Step S15 in FIG. 6, a first zincate treatment isperformed on the surface of the conductive film AL2.

As disclosed in “Zincate Treatment and Electroless Ni—P Plating on AlSingle-Crystal Surface,” Journal of The Surface Finishing Society ofJapan, Vol. 48, No. 8, p. 820-825, 1997, if ever the surface of theconductive film AL2 is (001) surface, growth of the zinc particles wouldbe less even and its size may further increase.

Next, as indicated at Step S16 in FIG. 6, the acid cleaning is performedon the surface of the conductive film AL2. For example, by using theaqueous solution containing nitric acid, zinc particles deposited by thefirst zincate treatment is dissolved in the aqueous solution containingnitric acid. This treatment allows aluminum to appear uniformly on thesurface of the conductive film AL2.

Next, as indicated at Step S17 in FIG. 6, a second zincate treatment isperformed on the surface of the conductive film AL2. This makes the zincparticles deposited onto aluminum again. A dense and uniform Zn film canbe formed by repeating the zincate treatment two times. This allows theplating film of nickel or the like that will be formed in the followingstep to be deposited uniformly.

Next, as indicated at Steps S18 to S20 in FIG. 6 and in FIG. 7, theelectroless plating treatment is performed on the surface of the padelectrode PD, thereby sequentially forming the conductive films PF1 toPF3.

First, as indicated at Step S18 in FIG. 6, the conductive film PF1containing mainly nickel (Ni) or the like is formed over the exposedsurface of the pad electrode PD (surface of the conductive film AL2) byelectroless plating. To form the conductive film PF1, the surface of theconductive film AL2 is immersed in plating aqueous solution containingnickel ion or the like. At this time, the zinc particles deposited bythe zincate treatment in FIG. 6 are dissolved into the plating aqueoussolution. At the same time, nickel is reduced and deposited by electronsemitted from the zinc particles. That is, in the region where the zincparticles are deposited, nickel is reduced and deposited and the platingfilm grows using the deposited nickel as catalyst, thereby forming theconductive film PF1. As described above, because the size of each zincparticle is small and constant, the substituted and deposited nickelfilm also grow uniformly. Thus, it is possible to improve uniformity ofthe thickness of the conductive film PF1.

Then, as indicated at Steps S19 and S20, by sequentially forming theconductive film PF2 containing mainly palladium (Pd) or the like and theconductive film PF3 containing mainly gold (Au) over the conductive filmPF1 by electroless plating, the conductive layer OPM including alamination of the plating films. Because the conductive film PF2 and theconductive film PF3 are formed over the conductive film PF1 havinghighly uniform thickness, the conductive film PF2 and the conductivefilm PF3 are also formed with highly uniform thickness. Thus, it ispossible to improve uniformity of thickness of the conductive layer OPM.

It is to be noted that the thickness of the conductive film PF1 is about1,000 to 4,000 nm, the thickness of the conductive film PF2 is about 100to 400 nm, and the thickness of the conductive film PF3 is about 30 to200 nm.

Because the conductive film PF1 is a principal film of the conductivelayer OPM, it is preferable to include a material having low sheetresistance. The conductive film PF3 is provided mainly to improveadhesiveness with an external connection terminal TR, and it ispreferable to include a material having higher adhesiveness to theexternal connection terminal TR than the conductive film PF1. Theconductive film PF2 is provided to prevent that the conductive film PF1be diffused over the surface of the conductive film PF3 to corrode aboundary between the conductive film PF1 and the conductive film PF3.

Moreover, the conductive layer OPM may be a lamination of the conductivefilm PF1 and the conductive film PF3 or a lamination of the conductivefilm PF1 and the conductive film PF2. Furthermore, the conductive filmPF1 and the conductive film PF2 may contain phosphorus (P).

In this manner, the conductive layer OPM including a plating film isformed over the pad electrode PD. It is to be noted that the conductivelayer OPM configures an anode electrode of the diode DI.

Next, a cathode region CT and a back electrode BE are formed on the backside of the semiconductor substrate SUB.

First, the back side of the semiconductor substrate SUB is polished toreduce the thickness of the semiconductor substrate SUB. Next, an n-typeimpurity is introduced from the back side of the semiconductor substrateSUB using ion implantation to form the cathode region CT having a higherimpurity concentration than that of the drift region DR. Subsequently,the introduced impurity is activated by heat treatment. Then, metalfilms including nickel (Ni), titanium (Ti), gold (Au), for example, aredeposited in this order from the side abutting the cathode region CTusing sputtering, thereby forming a cathode electrode (back electrode)BE including these metal films.

The semiconductor device according to the embodiment is manufactured inthe above-mentioned steps.

FIG. 8 is a schematic view showing one configuration in which asemiconductor wafer having the semiconductor device according to theembodiment formed thereon is diced into a chip CP1 by a dicing step of apost-processing treatment and then the semiconductor element includingthe diode DI according to the embodiment and an IGBT is modularized. Inthe schematic view, dimensions of configurations such as the conductivelayer OPM are different from those described with reference to FIG. 7.

In FIG. 8, the chip CP1 is the semiconductor device including the diodeDI according to the embodiment formed thereon, and a chip CP2 is thesemiconductor device including the semiconductor element of IGBT formedthereon.

The IGBT includes a configuration shown on the left side of FIG. 8. Asshown in FIG. 8, a p-type base layer 2 is formed over the surface of then-type semiconductor substrate that configures a drift region 1. Formedover the surface of the base layer 2 is an n-type source layer 3, andthe base layer 2 and the source layer 3 are coupled commonly to anemitter electrode 6 including an aluminum film or the like. The baselayer 2 arranged between the drift region 1 and the source layer 3 is achannel region, and a gate electrode 5 is formed over the channel regionvia a gate insulating film 4. Formed over the back side of the driftregion 1 are a buffer layer 7 doped with an n-type impurity, an emitterlayer 8 doped with a p-type impurity, and a collector electrode 9.

Moreover, as shown in FIG. 8, the cathode electrode BE of the diode DIand the collector electrode 9 of the IGBT are electrically coupled toeach other, and the anode electrode (conductive layer) OPM of the diodeDI and the emitter electrode 6 of the IGBT are also electrically coupledto each other.

FIGS. 9 and 10 show an example in which the chip CP1 and the chip CP2configuring the IGBT shown in FIG. 8 are packaged. FIG. 10 is across-sectional view taken along line A-A in the plan view shown in FIG.9. It is to be noted that a sealing resin MR and a die pad DP depictedin FIG. 10 are omitted in FIG. 9 for better understanding of the shapeof the external connection terminal TR. It is illustrated here that thechip CP1 and the chip CP2 are coupled in a single package using a clipincluding, for example, a copper sheet, as an example of the externalconnection terminal TR.

As shown in FIGS. 9 and 10, the chip CP1 and the chip CP2 are mountedover the die pad DP via a solder BP1. The die pad DP also serves as apower source potential terminal DT that supplies power source potentialto the chip CP1 and the chip CP2. That is, the cathode electrode BE ofthe chip CP1 and the collector electrode 9 of the chip CP2 areelectrically coupled to the power source potential terminal DT (die padDP) via the solder BP1.

Moreover, the external connection terminal TR is coupled to the CP1 andthe chip CP2 via a solder BP2. The external connection terminal TR iselectrically coupled to the ground potential terminal ST via aconductive adhesive or the like. The conductive layer OPM of the chipCP1 is coupled to the solder BP2. That is, the anode electrode(conductive layer) OPM of the chip CP1 and the emitter electrode 6 ofthe chip CP2 are electrically coupled to the ground potential terminalST via the solder BP2 and the external connection terminal TR.

Although detailed explanation is not provided, the gate electrode 5 ofthe IGBT is coupled to another terminal via a bonding wire or the likeother than the external connection terminal TR.

The chip CP1 and the chip CP2 coupled to the die pad DP and the externalconnection terminal TR are sealed with the sealing resin MR. In thismanner, the semiconductor device according to the embodiment ispackaged.

Moreover, the external connection terminal TR may be a bonding wireincluding copper or gold. However, for such a semiconductor device thathas a large area of the anode electrode (conductive layer) OPM of thediode DI and a large area of the emitter electrode 6 of the IGBT andthat is to receive voltage of hundreds of volts as in the embodiment, itis desirable to use a copper clip having a large area to reduceresistance related to coupling to another chip. It is also possible touse sintered silver (Ag) instead of the solders BP1, BP2.

Hereinbelow, main features of the embodiment are briefly summarized. Theembodiment is characterized in that the crystal surface on the surfaceof the conductive film AL2 is formed with the crystal surface differentfrom that of the crystal surface on the surface of the conductive filmAL1.

For example, when the crystal surface on the surface of the padelectrode PD is formed with the (001) surface, in the first and secondzincate treatments in FIG. 6, there is a problem that the size of thedeposited zinc particle is so large that the deposition of the platingfilm such as nickel formed by the electroless plating cannot beperformed uniformly and the surface of the plating film becomes rough.Thus, moisture or the like enters the interface between the padelectrode PD and the conductive layer OPM facilitating separation inthis portion, which reduces reliability of the semiconductor device.Furthermore, appearance abnormality is observed on the surface of theplating film.

To the contrary, in this embodiment, by forming the thin insulating filmBIF over the conductive film AL1 having the (001) surface, theconductive film AL2 formed over the insulating film BIF is not affectedby the crystal surface on the surface of the conductive film ALLallowing the he crystal surface on the surface of the conductive filmAL2 to have the (111) surface. Thus, because the size of each zincparticle deposited during the first and second zincate treatments shownin FIG. 6 is uniform and small, the deposite from the conductive filmPF1 including nickel and the like formed by electroless plating can beformed relatively uniformly. This allows for a configuration in whichseparation is hardly caused on the interface between the pad electrodePD and the conductive layer OPM, thereby improving reliability of thesemiconductor device. Furthermore, appearance abnormality on the surfaceof the plating film can be minimized.

Especially, in this embodiment, the cleaning treatment is performed onthe semiconductor substrate SUB serving as the base of the conductivefilm AL1 to keep the surface of the semiconductor substrate SUB clean.This reduces the contact resistance between the semiconductor substrateSUB and the conductive film ALL thereby reducing resistance of the diodeDI. However, because the conductive film AL1 tends to take over the(001) surface that is the crystal surface on the surface of thesemiconductor substrate SUB, the crystal surface on the surface of theconductive film AL1 also tends to have the (001) surface. Here, byforming the conductive film AL2 over the conductive film AL1 via theinsulating film BIF as described above, the crystal surface on thesurface of the conductive film AL2 may have the (111) surface, whichachieves the structure in which separation is hardly caused on theinterface between the pad electrode PD and the conductive layer OPM.That is, using the technique of the embodiment can improve performanceof the semiconductor device and also improve reliability of thesemiconductor device.

First Modification of First Embodiment

In the first embodiment, the insulating film BIF is formed over theconductive film AL1 by once taking out the semiconductor substrate SUBfrom the sputtering device and exposing it to the atmospheric air, asshown in FIG. 4.

To the contrary, according to a first modification, the semiconductorsubstrate SUB is transferred to another chamber without taking it out ofthe sputtering device, an oxygen-containing gas is introduced into thesputtering device, and the surface of the conductive film AL1 is exposedto oxygen atmosphere, thereby forming the insulating film BIF.Specifically, exposure to such oxygen atmosphere is performed in oxygengas atmosphere at room temperature. The oxidation treatment maybecombined with heat treatment, and may be conducted by emitting plasmausing oxygen gas.

Subsequently, the conductive film AL2 is formed over the insulating filmBIF by the sputtering as in the first embodiment, without taking out thesemiconductor substrate SUB from the sputtering device.

In this manner, because there is no need of taking out the semiconductorsubstrate SUB from the sputtering device to form the insulating filmBIF, it is possible to perform the next step of forming the conductivefilm AL2 immediately. Thus, compared with the first embodiment, it ispossible to simplify the process of manufacturing the semiconductordevice.

Second Modification of First Embodiment

In the first embodiment, the conductive film AL2 is configured using thesame material as that of the conductive film ALL the material containingmainly, for example, aluminum doped with silicon.

To the contrary, in a second modification, the conductive film AL2 isconfigured using a material different from that of the conductive filmAL1, the material containing mainly, for example, aluminum doped withcopper. That is, the element doped into the conductive film AL2 isdifferent from the element doped into the conductive film AL1.

The conductive film AL1 is in direct contact with the diode DI and madeof aluminum film doped with silicon for the purpose of reducing spikeshapes on the interface between the semiconductor substrate SUB and theconductive film AL1. However, because the conductive film AL2 is not indirect contact with the diode DI, the material of the conductive filmAL2 may be other material than the aluminum film doped with silicon.Here, because the copper-doped aluminum film exhibits betterelectromigration than the silicon-doped aluminum film, the copper dopedaluminum film is used as the conductive film AL2 of the secondmodification.

Moreover, by using the copper-doped aluminum film as the conductive filmAL2, the etching treatment at Step S13 in FIG. 6 can be omitted. Thatis, the aluminum oxide present over the surface of the conductive filmAL2 is substituted using the aqueous solution containing copper havinghigh standard electrode potential at Step S13 described above. However,in the second modification, copper is already included in the conductivefilm AL2. Therefore, it is possible to more effectively remove the oxideover the surface of the conductive film AL2 by the degreasing treatmentusing the alkaline aqueous solution at Step S12 or the subsequentzincate treatment. The zincate treatment further facilitates depositionof the zinc particles, and the electroless plating treatment furtherfacilitates substitute and deposite nickel. Thus, because Step S13 shownin FIG. 6 can be omitted in the second modification, the method ofmanufacturing the semiconductor device can be simplified.

Furthermore, the conductive film AL2 may be made of a materialcontaining mainly aluminum and doped with copper and silicon.

It is to be noted that the technique disclosed in the secondmodification is also applicable to the above-mentioned firstmodification.

Second Embodiment

In the first embodiment, the insulating film BIF is formed over theconductive film AL1 to differentiate the crystal surface of theconductive film AL2 from that of the conductive film ALL

To the contrary, in the second embodiment, formed over the conductivefilm AL1 is an amorphous film that is a conductive film made of amaterial different from that of the conductive film AL1 and in anamorphous state over the conductive film AL1. It is to be noted that theamorphous film a replacement from the insulating film BIF in the firstembodiment and therefore it is not presented in the drawings. In otherwords, the reference symbol “BIF” indicated in FIG. 4 or the likedesignates the amorphous film.

Such an amorphous film is formed by sputtering or CVD and configured bya film containing mainly, for example, tantalum, titanium nitride, ortungsten nitride. Moreover, the thickness of the amorphous film isbetween 0.5 nm and 4.0 nm, and more preferably between 1.0 nm and 3.0nm.

That is, the above-mentioned material can exist in the amorphous stateas long as it has such a small film thickness. Because the amorphousfilm is in the amorphous state, it does not have a specific crystalsurface. Therefore, when the conductive film AL2 is formed over theamorphous film by sputtering, the conductive film AL2 does not take overthe crystal surface of the conductive film AL1 but grows mainly based onthe (111) surface, as in the first embodiment. That is, the amorphousfilm is an orientation blocking film serving as a film for blockingorientation of crystal, like the insulating film BIF. Thus, thesemiconductor device according to the second embodiment can provide thesame effect as the first embodiment.

It is to be noted that the second modification of the first embodimentdescribed above can be applied to the technique disclosed in the secondembodiment.

Third Embodiment

In a third embodiment, the conductive film AL1 and the conductive filmAL2 used in the first embodiment are applied to wiring of a power MOS.Here, as an example of the wiring of the power MOS, a case is describedin which the conductive film AL1 and the conductive film AL2 are appliedto a source electrode SPD.

A structure of the semiconductor device according to the thirdembodiment and a method of manufacturing the same are described belowwith reference to FIGS. 11 to 13.

FIG. 11 shows an n-type power MOS including an n-type gate electrode GE,a gate insulating film GI, an insulating film IF3 that covers the gateelectrode GE, a p-type channel region CH, an n-type source region SR, ann-type drift region NV serving as a drain region, and an n-typesubstrate SB.

An example method of manufacturing such a power MOS is described below.

The substrate SB having n-type conductivity and including semiconductorsuch as silicon is prepared first. Next, a drift region NV (impurityregion NV) having n-type conductivity and impurity concentration lowerthan that of the substrate SB is formed over the substrate SB by epitaxyor the like. In this embodiment, explanation is given assuming astructure including the substrate SB and the drift region NV as thesemiconductor substrate SUB.

After forming a groove in the drift region NV, a gate insulating film GIincluding silicon oxide is formed over the side face and the bottom faceof the groove. Next, the gate electrode GE including polycrystallinesilicon or the like is formed over the gate insulating film GI so as tofill the groove. Then, the channel region CH having p-type conductivityis formed on top of the drift region NV by ion implantation. A boundarybetween the channel region CH and the drift region NV is located abovethe bottom face of the gate electrode GE. The source region SR (impurityregion SR) having n-type conductivity is then formed on top of thechannel region CH by ion implantation. The insulating film IF3 is thenselectively formed over a portion of the source region SR and over thegate electrode GE. Next, by performing dry etching on a portion exposedon the insulating film IF3, an opening OP2 reaching the channel regionCH through the source region SR is formed. The n-type power MOS ismanufactured as described above.

Next, as shown in FIG. 12, the conductive film AL1 and the conductivefilm AL2 serving as the source electrode SPD are formed over theinsulating film IF3.

First, a barrier metal film BM including titanium tungsten (TiW),titanium nitride (TiN), or the like is formed in the opening OP2 andover the insulating film IF3. Then, the conductive film AL1 containingmainly aluminum, for example, is formed over the barrier metal film BMso as to fill the opening OP2. This allows the conductive film AL1serving as a part of the source electrode SPD to be electrically coupledto the source region SR and the channel region CH.

It is to be noted that, in the third embodiment, the barrier metal filmBM is formed between the semiconductor substrate SUB and the conductivefilm AL1 unlike the first embodiment and the second embodiment describedabove. Accordingly, the conductive film AL1 may use a material mainlycontaining aluminum and doped with silicon or a material mainlycontaining aluminum and doped with copper.

Here, the conductive film AL1 is formed by sputtering, and the maximumtemperature in the forming process ranges from 250 to 400 degrees, whichis higher than that in the first embodiment. This is to prevent a voidformed in the conductive film AL1 when the conductive film AL1 is filledin the opening OP2. The formation of the conductive film AL1 may beperformed in two steps including an initial film formation performed ata low temperature ranging from room temperature (23° C.) to 200° C. anda second step performed at a high temperature ranging from 250 to 400°C. for filling. Moreover, a step is made between the surface of theconductive film AL1 located on top of the opening OP2 and the surface ofthe conductive film AL1 located on top of the gate electrode GE. Tominimize the step to make the entire surface of the conductive film AL1as flat as possible, it is effective to form the conductive film AL1 athigh temperature. For the semiconductor device according to thisembodiment, the conductive layer OPM is formed over the source electrodeSPD in a later step. Thus, by eliminating any void in the conductivefilm AL1 serving as apart of the source electrode SPD and flattening itssurface, it is possible to make the thickness of the conductive layerOPM more uniform.

In such an aluminum film formed at relatively high temperature, however,the size of the aluminum particle tends to be larger compared with analuminum film formed at relatively low temperature as in the firstembodiment. That is, the crystal surface on the surface of theconductive film AL1 tends to have not only the (111) surface but alsothe (001) surface. Thus, if the conductive layer OPM is formed over theconductive film AL1, separation would easily occur between the sourceelectrode SPD and the conductive layer OPM as in the first embodiment.

Therefore, in the third embodiment, the thin insulating film BIF isformed over the conductive film AL1 and then the conductive film AL2 isformed over the conductive film AL1 as in the first embodiment. This candifferentiate the crystal surface on the surface of the conductive filmAL2 from the crystal surface on the surface of the conductive film AL1.It is to be noted that the method of forming the insulating film BIF andthe conductive film AL2 is the same as that in the first embodiment.Accordingly, the crystal surface on the surface of the conductive filmAL2 in this embodiment is also the (111) surface.

In this embodiment, the temperature of formation of the conductive filmAL2 is lower than that of the conductive film ALL and it is about roomtemperature (23° C.) to 200° C., for example, and more preferably about150° C. That is, because the conductive film AL1 is formed at relativelyhigh temperature, the flatness of its surface is improved whereas thepossibility of generating the (001) surface having a large particle sizealso increases. Therefore, generation of the (001) surface having thelarge particle size can be suppressed by forming the conductive film AL2at relatively low temperature. In other words, in the third embodiment,the area ratio of the (111) surface on the surface of the conductivefilm AL2 is higher than that of the (111) surface on the surface of theconductive film AL1

Then, the source electrode SPD shown in FIG. 12 is formed by patterningthe conductive film AL2, the insulating film BIF, the conductive filmALL and the barrier metal film BM using photolithography and dryetching. It is to be noted that a gate pad electrode GPD to be coupledto the gate electrode GE of the power MOS is also formed at this time(not shown in the figure).

Next, as shown in FIG. 13, the insulating film IF2 having the openingOP1 is formed over the conductive film AL2 so as to expose a portion ofthe conductive film AL2 serving as a portion of the source electrodeSPD. It is to be noted that the method of forming the insulating filmIF2 and its material are the same as those in the first embodiment.

Next, by sequentially forming the conductive films PF1 to PF3 using thesame technique as in the first embodiment, the conductive layer OPM isformed over the conductive film AL2 in the opening OP1.

Then, as in the first embodiment, the back side of the substrate SB ispolished to form the drain electrode (back electrode) BE.

The semiconductor device of the third embodiment is manufacturedaccording to the above-mentioned steps.

As described above, according to the third embodiment, it is possible tosuppress the separation between the source electrode SPD and theconductive layer OPM and to obtain the same effect as the firstembodiment.

FIG. 14 shows a view of a chip CP3 including the power MOS according tothe third embodiment formed thereon in the packaged state. Here, as anexample of the external connection terminal TR to be coupled to theconductive layer OPM, a case of using a clip made of a copper sheet isdescribed.

As shown in FIG. 14, the chip CP3 is mounted over the die pad DP via asolder BP3. The die pad DP also serves as the power source potentialterminal DT that supplies power source potential to the chip CP3. Thatis, the drain electrode BE of the chip CP3 is electrically coupled tothe power source potential terminal DT (die pad DP) via the solder BP3.

Moreover, the external connection terminal TR is coupled to the chip CP3via a solder BP4. The external connection terminal TR is electricallycoupled to the ground potential terminal ST via a solder BP5. Here, theconductive layer OPM of the chip CP3 is coupled to the solder BP4. Thatis, the source electrode SPD of the chip CP3 is electrically coupled tothe ground potential terminal ST via the conductive layer OPM, thesolder BP4, the external connection terminal TR, and the solder BP5.

Moreover, the gate pad electrode GPD of the power MOS is coupled to agate potential terminal GT via a bonding wire WB.

Such a chip CP3 is sealed with the sealing resin MR. In this manner, thesemiconductor device according to the third embodiment is packaged.

Furthermore, it is also possible to apply the technique of the first andsecond modifications of the first embodiment and the second embodimentto the technique disclosed in the third embodiment.

Moreover, although the conductive film AL1 and the conductive film AL2are employed as the source electrode SPD of the power MOS in the thirdembodiment, it is also possible to employ the conductive film AL1 andthe conductive film AL2 as the emitter electrode of the IGBT.Furthermore, when applied to the IGBT, the channel region CH of thepower MOS is a base region.

Moreover, when applying the technique disclosed in the third embodimentto the IGBT, the chip CP3 described in the third embodiment maybeemployed instead of the chip CP2 shown in FIGS. 8 to 10 of the firstembodiment.

Although the invention made by the inventors are specifically describedwith reference to the embodiments, the invention is not limited to theembodiments but various modifications may be made without departing fromthe scope of the invention.

What is claimed is:
 1. A semiconductor device comprising: a padelectrode that is formed over a semiconductor substrate and comprises afirst conductive film and a second conductive film formed over the firstconductive film; and a plating film that is formed over the secondconductive film and serves to be coupled to an external connectionterminal, wherein each of the first and second conductive filmscomprises a film containing mainly aluminum, and wherein a crystalsurface on a surface of the second conductive film is different from thecrystal surface on the surface of the first conductive film.
 2. Thesemiconductor device according to claim 1, wherein the second conductivefilm is in direct contact with the plating film, and wherein the crystalsurface on the surface of the second conductive film is a (111) surface.3. The semiconductor device according to claim 2, wherein a firstinsulating film comprising an oxide of a material that configures thefirst conductive film is formed between the first conductive film andthe second conductive film.
 4. The semiconductor device according toclaim 2, wherein an amorphous film comprising a material different fromthat of the first conductive film and the second conductive film isformed between the first conductive film and the second conductive film.5. The semiconductor device according to claim 2, wherein an elementdoped into the second conductive film is different from an element dopedinto the first conductive film.
 6. The semiconductor device according toclaim 2, wherein the semiconductor substrate comprises a diode formedthereon, wherein a surface of semiconductor substrate provided with thediode is in direct contact with the first conductive film, and wherein acrystal surface on a surface of the semiconductor substrate and acrustal surface on a surface of the first conductive film are a (001)surface.
 7. The semiconductor device according to claim 2, wherein anarea ratio of the (111) surface on the surface of the second conductivefilm is higher than that of the (111) surface on the surface of thefirst conductive film.
 8. The semiconductor device according to claim 7,wherein the semiconductor substrate comprises a power MOSFET formedthereon, and wherein a source electrode of the POWER MOSFET comprisesthe first conductive film and the second conductive film.
 9. A method ofmanufacturing a semiconductor device, comprising the steps of: (a)forming a first conductive film over a semiconductor substrate bysputtering; (b) forming a second conductive film over the firstconductive film by sputtering; (c) providing a pad electrode bypatterning on the first conductive film and the second conductive film;and (d) forming a plating film for coupling to the external connectionterminal over the pad electrode by electroless plating, wherein each ofthe first and second conductive films comprises a film containing mainlyaluminum, and wherein a crystal surface on a surface of the secondconductive film is different from the crystal surface on the surface ofthe first conductive film.
 10. The method of manufacturing asemiconductor device according to claim 9, wherein the second conductivefilm is in direct contact with the plating film, and wherein the crystalsurface on the surface of the second conductive film is a (111) surface.11. The method of manufacturing a semiconductor device according toclaim 10, further comprising the step of: (e) forming a first insulatingfilm over the first conductive film between the steps of (a) and (b) byexposing a surface of the first conductive film to oxygen atmosphere.12. The method of manufacturing a semiconductor device according toclaim 11, wherein the step (e) is performed by taking out thesemiconductor substrate from a sputtering device and expose thesemiconductor substrate to atmospheric air.
 13. The method ofmanufacturing a semiconductor device according to claim 11, wherein thestep (e) is performed by introducing oxygen gas into the sputteringdevice without taking out the semiconductor substrate from thesputtering device used at the step (a), and wherein the step (b) isperformed without taking out the semiconductor substrate from thesputtering device after the step (e).
 14. The method of manufacturing asemiconductor device according to claim 11, further comprising the stepof: (f) forming an amorphous film over the first conductive film bysputtering or CVD between the steps (a) and (b).
 15. The method ofmanufacturing a semiconductor device according to claim 10, wherein anelement doped into the second conductive film is different from anelement doped into the first conductive film.
 16. The method ofmanufacturing a semiconductor device according to claim 10, wherein thesemiconductor substrate comprises a diode formed thereon, wherein acleaning treatment is performed on a surface of the semiconductorsubstrate having the diode formed thereon before the step (a), whereinthe first conductive film is formed to be in direct contact with thesurface of the semiconductor substrate at the step (a), and wherein acrystal surface on a surface of the semiconductor substrate and acrustal surface on a surface of the first conductive film are a (001)surface.
 17. The method of manufacturing a semiconductor deviceaccording to claim 10, wherein temperature for forming the firstconductive film is higher than temperature for forming the secondconductive film, and wherein an area ratio of the (111) surface on thesurface of the second conductive film is higher than that of the (111)surface on the surface of the first conductive film.
 18. The method ofmanufacturing a semiconductor device according to claim 17, wherein thesemiconductor substrate comprises a power MOSFET formed thereon, andwherein a source electrode of the POWER MOSFET comprises the firstconductive film and the second conductive film.
 19. The method ofmanufacturing a semiconductor device according to claim 10, wherein azincate treatment is performed two times between the steps (c) and (d).20. The method of manufacturing a semiconductor device according toclaim 19, wherein the plating film contains mainly nickel.